1. Field of the Invention
The present invention relates to a digital semiconductor integrated circuit of a CMOS (complementary metal oxide semiconductor field effect transistor) structure, and more specifically to a semiconductor integrated circuit provided with a test circuit for checking whether or not a threshold voltage of an input buffer is within a predetermined range.
2. Description of Related Art
Ordinarily, a semiconductor integrated circuit (called an "LSI" hereinafter) is so configured that a plurality of digital data signals and control signals are simultaneously received, and a predetermined signal processing is performed by an internal logic circuit (called an "internal circuit" simply hereinafter). In this case, before a signal supplied to each of external terminals for receiving a signal (input terminals) is applied to the internal circuit, each input signal is current-amplified by an input buffer to have a sufficient driving power, and thereafter, the input signal is actually applied to the internal circuit. Therefore, in order to cause the LSI to execute an expected signal processing, each input buffer is required to transfer a logic value of the input signal to the internal circuit without error. As one requirement for fulfilling this request, it is very important that a threshold voltage of the input buffer is in a predetermined range.
In a conventional test for the threshold of the input buffer in the LSI, a test signal is applied to an input terminal (an input point of the input buffer) so as to perform a function test of the LSI. If the LSI operates normally, namely, if an expected output signal is obtained from an external output terminal of the LSI, it is discriminated that the threshold voltage of the input buffer meets with the standard value. In this case, however, depending upon a combination of input signals applied to a plurality of input buffers, it is in some cases that a signal applied to an input buffer to be tested is used only for the signal processing in the internal circuit, and the change of the input signal is not externally outputted as any change of a signal outputted from an output terminal. In this case, the input threshold of the input buffer in question cannot be tested. Therefore, in order to surely test the threshold of the input buffer in question, it was necessary to repeat the function test while variously changing a combination of the input signals applied to a plurality of input terminals. Recently, with a remarkable advance of the integration density and the multi-function of the LSI, the number of the input terminals has increased, and therefore, a function test pattern for testing the input threshold voltage of all input buffers becomes very complicated and large and long. Therefore, the number of steps for preparing and actually performing the function test pattern has increased, and this increased number of steps has become a large problem.
Under this circumstance, the prior art has proposed various methods and apparatuses for efficiently performing the input threshold voltage. Japanese Patent Application Pre-Examination Publication JP-A-3-214079 proposes one approach (called a "first prior art" hereinafter). Referring to FIG. 1A, there is shown a block diagram of the input threshold voltage measuring apparatus shown in JP-A-3-214079. FIG. 1B illustrates an operation waveform at the time of the measurement.
In the input threshold voltage measuring apparatus shown in FIG. 1A, a sweep voltage generating circuit 801 generates an analog sweep voltage waveform "s" shown in an upper part of FIG. 1B. This voltage waveform "s" is a truncated conical shape having two ramp voltages, which, with lapse of a time, firstly elevates constantly at a predetermined rate, and then, becomes flat, and finally, drops constantly at a predetermined rate. This sweep voltage generating circuit 801 is constituted of a ROM 802, a D/A converter 803, and a control circuit 804 accessing the ROM 802.
In the ROM 802, digital data to be converted into an analog voltage at each moment in order to generate the analog sweep voltage waveform "s" is stored in a sequential address in order.
The control circuit 804 is composed of a clock generator and a program counter (both not shown) for generating an address used to access the ROM 802, so that the ROM 802 is accessed in accordance with the address generated. The access address is sequentially incremented in response to the clock. Thus, the digital data to be converted into an analog value is read out from respective addresses of the ROM, with lapse of time in units of a clock period, so that the read-out digital data is supplied to the D/A converter 803. As a result, the analog sweep voltage waveform "s" is outputted from the D/A converter 803.
In addition, if the control circuit 804 receives a sweep stop signal from a peak current detecting circuit 808 explained hereinafter, the control circuit stops the increment of the address counter in response to the clock generated by the clock generator. In this condition, the address in a stopped position of the ROM 802 is repeatedly continuously accessed in response to the clock, so that the digital data at the stopped address is continuously supplied to the D/A converter 803. Thus, the analog voltage generated at the moment the sweep stop signal is received, continues to be outputted from the sweep voltage generating circuit 801.
The analog voltage thus generated by the sweep voltage generating circuit 801 is applied through a switch circuit 805 to one of input terminals IN of an integrated circuit 806, namely, a device under test (abbreviated "DUT" hereinafter). The switch circuit 805 is a change-over switch controlled by a switch change signal from the peak current detecting circuit 808, so as to switch the output voltage of the sweep voltage generating circuit 801 from the DUT 806 to a voltage measuring circuit 807.
The peak current detecting circuit 808 is a current level detecting circuit composed of a comparator, and operates to generate a detection signal when a current IDD flowing from a power supply circuit 809 to a power supply terminal VDD of the DUT 806 exceeds a predetermined reference level ITH (See FIG. 1B). This detection signal is supplied as the sweep stop signal D to the sweep voltage generating circuit 801, and also as the switch change signal to the switch circuit 805. In addition, the detection signal D is supplied as a peak detection signal to a measurement control circuit 810.
The measurement control circuit 810 supplies a start signal to the sweep voltage generating circuit 801, and receives and processes a measured voltage value obtained in the voltage measuring circuit 807. Thus, it is a control circuit for the whole of the input threshold voltage measuring apparatus.
Now, operation of the first prior art having the above mentioned construction will be described with reference to FIG. 1B.
First, the measurement control circuit 810 outputs the start signal to the sweep voltage generating circuit 801. In response to the start signal, the sweep voltage generating circuit 801 generates the analog sweep voltage waveform "s" shown in FIG. 1B, so that the input voltage Vin of the DUT 806 linearly elevates with a lapse of time. When the analog voltage "s" exceeds an input threshold voltage of the input buffer of the DUT 806, the internal circuit receiving this input signal is put in an operating condition. At this time, depending upon the operation of the internal circuit, a transient current flows as an operating current for example in a CMOSIC. This operation current IDD is measured as a characteristics current curve "p" having a peak shown in FIG. 1B.
This current value IDD is monitored by the peak current detecting circuit 808. The moment the current value IDD exceeds the reference current value ITH, corresponds to the moment an inverter (constituting the input buffer in the DUT 806) flips. Therefore, this means that the voltage waveform "s" exceeds the input threshold voltage. In the shown example, the peak current detecting circuit 808 generates the peak current detecting signal at a time T901. The sweep voltage generating circuit 801 receiving the detecting signal as the sweep stop signal D, stops the sweep operation, and at the same time, the switch circuit 805 is switched over so that the analog voltage generated by the sweep voltage generating circuit 801 at that time is measured through the switch circuit 805 by the voltage measuring circuit 807. The result of the measurement is fetched into the measurement control circuit 810 receiving the peak the detecting signal D.
At this time, the measurement control circuit 810 supplies a control signal to the sweep voltage generating circuit 801 so as to cancel the clock stop signal. As a result, after the sweep voltage has become a constant value, the sweep voltage starts to drop.
In the course of the drop of the sweep voltage, when the value of the voltage waveform "s" becomes lower than the input threshold voltage of the DUT 806, a peak current appears again in the current IDD. With this, it is possible to measure a low level VIL of the input threshold voltage.
Incidentally, this first prior art is so configured that the reference value ITH used as the comparison reference in the peak current detecting circuit 808 can be adjusted externally so as to be changed in accordance with the characteristics of the DUT 806.
Next, another example of the conventional input threshold voltage testing method disclosed in Japanese Patent Application Pre-Examination Publication JP-A-4-194667 (called a "second prior art" hereinafter).will be described with reference to FIG. 2A.
Referring to FIG. 2A, an input circuit 1021 of a Bi-CMOS LSI is supplied with a supply voltage VDD through an ammeter 1023, and an input voltage Vin is applied to an input terminal 1020 from a DC voltage supply 1022.
Here, when the input voltage Vin is for example at a low level, a pnp transistor 1006 is in an on condition, and therefore, a p-channel MOS (pMOS) transistor 1007 is also in an on condition and an n-channel MOS (nMOS) transistor 1008 is in an off condition, so that an output voltage at a terminal 1024 is at a high level. Thereafter, if the input voltage Vin is caused to gradually elevate as shown in FIG. 2B, the pnp transistor 1006 is brought to an off condition from the on condition. At this time, before the pMOS transistor 1006 is completely turned off, the nMOS transistor 1008 is turned on, so that a passthrough current flows from the voltage supply terminal VDD to a ground terminal GND as shown in FIG. 2C. Thereafter, the pMOS transistor 1007 is turned off, and the nMOS transistor 1008 is turn on, so that the output voltage on the terminal 1024 is brought to a low level.
Thus, the input voltage Vin when the ammeter 1023 detects the above mentioned passthrough current, corresponds to the threshold voltage Vth. Accordingly, the input threshold voltage is measured by detecting the passthrough current which flows in the input circuit operation when the input voltage Vin is gradually changed.
Now, a third example of the conventional input threshold voltage testing method will be described on the basis of the disclosure of in Japanese Utility Model Application Pre-Examination Publication JP-UA-2-007580 (called a "third prior art" hereinafter).
Referring to FIG. 3A, there is shown an apparatus for discriminating a non-defective/defective of a DUT incorporating a plurality of electronic circuits therein, on the basis of an input threshold voltage. This apparatus includes an input voltage generator 1214 for supplying an input voltage into each of input circuits 1212 of the DUT 1210, a passthrough current detecting circuit 1215 for detecting a passthrough current which instantaneously flows in the input circuits when an output level of each input circuit 1212 changes in response to the input voltage, and a threshold voltage discriminator 1222 for discriminating on the basis of the passthrough current, whether or not the threshold voltage of the input voltage is in a standardized range.
As shown in FIG. 3B, the input voltage generator 1214 receives a test start signal 1213 and gradually elevates the input voltage Vin from a low level to a high level. In this process, when the input voltage Vin exceeds the input threshold of the input circuit 1212 internally provided in the DUT 1210, the output voltage Vout of the input circuit 1212 is brought from a low level to a high level. At this time, a passthrough current as mentioned hereinbefore is detected by the passthrough current detecting circuit 1215, which outputs a passthrough current detecting signal 1211 to the threshold voltage discriminator 1222. This threshold voltage discriminator 1222 receives the passthrough current detecting signal 1211, and discriminates whether or not the threshold voltage of the input voltage is in the standardized range. Namely, the threshold voltage discriminator 1222 outputs the result of the discrimination. Thus, the input threshold voltage test is performed.
All of the first, second and third prior arts explained above are so configured to measure the input threshold voltage of the input circuit by detecting the increase of the power supply current (generation of the passthrough current in the input circuit) when the input voltage exceeds the threshold voltage of the input buffer and the circuit including the input buffer changes its condition. Differently from the above mentioned prior arts, another approach is to set, a mode generally called a test mode, different from a mode in which inherent signal processing is performed in which a threshold voltage of the input buffer is tested and measured by using an input voltage testing circuit provided in the LSI. In the following, some of this type approach will be described.
Now, as a fourth example of the conventional input threshold voltage testing approach, a construction of the LSI disclosed in Japanese Patent Application Pre-Examination Publication JP-A-4-359175 (called a "fourth prior art" hereinafter).will be described with reference to FIGS. 4A and 4B.
Referring to FIG. 4A, there is shown a block diagram of the LSI incorporating therein a circuit for measuring the input threshold voltage of the input buffer and for outputting the result of the measurement. As shown in FIG. 4A, an input signal applied to an input terminal 1408 is supplied to an input buffer 1402. An output signal of the input buffer 1402 is supplied to an internal circuit 1401 where various electric circuits are caused to operate. At the same time, the output signal of the input buffer 1402 is supplied to a selector 1404 as one signal to be selected.
The selector 1404 receives, as another signal to be selected, an output signal 1406 from the internal circuit 1401, and is controlled by a selector selection signal 1407 generated in the internal circuit 1401, so as to select and output one of the two "signals to be selected" supplied to the selector 1404. The selected signal is supplied to an output buffer 1403, which in turn outputs the supplied signal through an output terminal 1409 to an external of the LSI.
When the input threshold value is tested, the selector selection signal 1407 controls the selector 1404 to select the signal 1405 to be selected and to output it to the output buffer 1403. In a normal signal processing operation, the selector selection signal 1407 controls the selector 1404 to select the signal 1406 to be selected so that information is transferred from the internal circuit 1401 to the output buffer 1403.
When the input threshold voltage test is executed, a standardized voltage VIH of a high level input threshold voltage is applied to the input terminal 1408, as shown in an upper column of FIG. 4B. This input signal causes the input buffer 1402 to operate, so that the output signal 1405 of the input buffer is selected by the selector 1404 to be transferred to the output buffer 1403. If the input threshold voltage of the input buffer 1402 meets with the above mentioned standardized voltage VIH of the high level input threshold voltage, an output signal in the same phase as that of the input signal appears on the output terminal 1409, as shown in a middle column of FIG. 4B. However, when the input threshold voltage of the input buffer 1402 does not meet with the standardized voltage, namely, when the input buffer 1402 malfunctions, an output signal in a phase opposite to that of the input signal appears on the output terminal 1409, as shown in a lower column of FIG. 4B. In this manner, whether or not the input threshold voltage fulfills the standard, can be discriminated on the basis of whether the input signal and the output signal are in the same phase or in the opposite phase.
Next, as a fifth example of the conventional input threshold voltage testing approach, a construction of the LSI disclosed in Japanese Patent Application Pre-Examination Publication JP-A-2-291164 (called a "fifth prior art" hereinafter).will be described with reference to FIGS. 5A and 5B.
Referring to FIG. 5A, an input node of an input buffer 1604 is connected to an input terminal 1601, and an input node of input buffers 1605 and 1606 are connected to input terminals 1602 and 1603, respectively.
An output node of the input buffer 1604 is connected to an internal circuit 1610 and one input "A" of a two-input NAND gate 1607, which in turn has the other input "B" connected to a voltage supply terminal VDD. An output node of the input buffer 1605 is connected to the internal circuit 1610 and one input "A" of another two-input NAND gate 1608, which in turn has the other input "B" connected to an output of the NAND gate 1607. An output node of the input buffer 1606 is connected to the internal circuit 1610 and one input "A" of a further two-input NAND gate 1609, which in turn has the other input "B" connected to an output of the NAND gate 1608. An output of the NAND gate 1609 is connected to an external output terminal 1617.
Now, an input threshold voltage testing method in this LSI will be described with reference to a timing chart shown in FIG. 5B. The input threshold of the input buffer 1604 is tested during a period T171 in FIG. 5B. During this period, the input terminals 1602 and 1603 are fixed to a high level (supply voltage), and the input level of the input terminal 1601 is brought to a standardized voltage VIH of a high level threshold voltage. At this time, if the input buffer 1604 operates normally, the output signal 1611 of the input buffer 1604 becomes a high level, and therefore, the output of the NAND gate 1607 becomes a low level. Here, since the input terminals 1602 and 1603 are at the high level, both the output signal 1612 of the input buffer 1605 and the output signal 1613 of the input buffer 1606 are at the high level. Therefore, the NAND gates 1607, 1608 and 1609 become equivalent to an inverter chain receiving the signal 1611 as an input signal and for outputting a signal 1616 as an output signal.
In the shown example, since the three input terminals are provided, the output signal 1616 is in a phase opposite to that of the input terminal 1601, and the output terminal 1617 outputs a low level signal as shown in a fourth row of FIG. 5B. Similarly, when the input level of the input terminal 1601 is brought to a standardized voltage VIL of a low level threshold voltage, if the input buffer 1604 operates normally, the output terminal 1617 outputs a high level signal as shown in the fourth row of FIG. 5B.
On the contrary, if the input buffer 1604 malfunctions, the signal 1611 becomes in a phase opposite to that of the input level, and therefore, the output terminal 1617 outputs a signal having the same phase as that of the input level, as shown in a fifth row of FIG. 5B.
Next, during a period T172 in FIG. 5B, the input threshold of the input buffer 1605 is tested. At this time, the input terminal 1603 is maintained at the high level, but the input terminal 1601 is maintained at the low level. By setting the input terminals as mentioned above, the output 1611 of the input buffer 1604 becomes the low level, so that the output 1614 of the NAND gate 1607 becomes the high level. Thus, the NAND gates 1608 and 1609 becomes equivalent to an inverter chain of two stages receiving the signal 1612 as an input signal and for outputting the signal 1616 as an output signal.
Therefore, if the input buffer 1605 operates normally, a signal appearing on the output terminal 1617 is in the same phase as that of the input signal applied to the input terminal 1602. On the contrary, if the input buffer 1605 malfunctions, the signal appearing on the output terminal 1617 is in a phase opposite to that of the input level applied to the input terminal 1602.
Next, during a period T173 in FIG. 5B, the input threshold of the input buffer 1606 is tested. At this time, the input terminal 1602 is maintained at the low level, but the input terminal 1603 may be at the low level or at the high level. By setting the input terminals as mentioned above, the output 1612 of the input buffer 1605 becomes the low level, so that the output 1615 of the NAND gate 1608 becomes the high level. Thus, the NAND gate 1609 becomes equivalent to an inverter receiving the signal 1613 as an input signal and for outputting the signal 1616 as an output signal.
Therefore, if the input buffer 1606 operates normally, the signal appearing on the output terminal 1617 is in a phase opposite to that of the input signal applied to the input terminal 1603. On the contrary, if the input buffer 1605 malfunctions, the signal appearing on the output terminal 1617 is in the same phase as that of the input signal applied to the input terminal 1602.
Thus, it is possible to discriminate whether or not each of the input buffer operates normally, on the basis of whether the output signal is in the same phase as that of the input signal or in the opposite phase to that of the input signal.
In the conventional examples mentioned above, the input threshold voltage test methods of the first to third prior arts are configured to applying a ramp voltage to the input node of the input buffer and to detect the passthrough current flow when the ramp voltage exceeds the threshold of the input buffer, as an increase of the power supply current. However, when these methods are applied to the testing of an LSI having a plurality of input terminals, it is impossible to clearly define a reference current value used for discriminating the increase of the power supply current. Actually, there is no LSI having only one input terminal. Namely, if it is considered that actual LSIs have a number of input terminals, it can be said that the input threshold voltage test methods of the first to third prior arts cannot actually discriminate the non-defective/defective of the input threshold voltage of the LSIs. The reason for this is as follows:
Now, assume that, in accordance with the first to third prior arts, the input threshold voltage test is performed for input buffers of an LSI having two external input terminals A and B. Here, the two input buffers will be called an input buffer A and an input buffer B, respectively.
FIG. 6A illustrates an operation at the time of the measurement. In FIG. 6A, the axis of abscissas shows a time, and the axis of ordinates indicates an input voltage applied to the input terminals A and B. In addition, it is assumed that a high level input threshold voltage of the input buffer A is VA, a high level input threshold voltage of the input buffer B is VB, and a standardized value of the high level input threshold voltage is VH Therefore, the input buffer A fulfills the standardized value VH, and on the other hand, the input buffer B does not fulfill the standardized value VH. The voltage waveform "s" shows that the voltage applied to the input buffers A and B gradually elevates with the lapse of time. In FIG. 6B, on the other hand, the axis of abscissas shows a time with the same scale as that of the axis of abscissas of FIG. 6A, and the axis of ordinates indicates the power supply current of the LSI. The current value ITH is a reference current value used for the comparison in order to discriminate whether or not an increase of the power supply current occurs when the input voltage applied to each input terminal exceeds the input threshold of a corresponding input buffer.
Referring to FIGS. 6A and 6B, at a time t18A, the input buffer B flips for the first time, so that an operation current flows, and therefore, the power supply current increases. In the first to third prior arts, the value of the power supply current at the time t18A must be compared with the reference current value. In other words, as the input threshold voltage, the input voltage at the time that the operation current is detected the voltage applied to the input terminals A and B gradually elevates. Because, during a period t18E after the first input buffer flips, an internal circuit receiving an output signal of the input buffer B and its succeeding circuits operate so that the power supply current further increases. Therefore, it is not possible to recognized that, in the change of the power supply current after the time t18A, the power supply current at a time t18B is attributable to the operating current of the input buffer A which flips lastly since it have the highest input threshold. However, in the high level input threshold voltage testing, it is necessary to discriminate whether or not the input buffer having the highest input threshold fulfills the standardized value. Therefore, the test in accordance with the first to third prior arts cannot make a proper discrimination.
The above mentioned situation is not any special case. Rather, it can be said that there is no LSI having only one input terminal. Therefore, it must be said that the first to third prior arts cannot be used for an ordinary GO/NOGO testing, nor can it be used to measure a "true capability value" of the worst input threshold voltage (a distribution of the worst input threshold voltage of LSIs when a number of LSI is tested).
Next, the fourth prior art shown in FIG. 4A is so configured that the output buffer 1403 for outputting the signal 1406 indicative of the result of the signal processing in the normal mode is used as the output buffer even in the test mode, so that the output signal 1405 of the input buffer 1402 is outputted through the output buffer 1403 to the external. In this method, in the case that the number of output buffers is smaller than the number of input buffers, extra output buffers which are not required for the signal processing in the normal mode, must be added for only the input threshold voltage test. This results in an increase in the number of external terminals, and therefore, makes the size of the LSI large and lowers the package density of the LSI.
On the other hand, in the fifth prior art, the expected value of the output logic value for discriminating the non-defective/defective changes dependently upon an input buffer to be tested. In addition, for each input buffer to be tested, it is necessary to change the logic value applied to the input terminals other than to the input terminal connected to the input buffer to be tested. Therefore, how to change the input signal to be applied to the input terminal and the expected output value for the discrimination depend upon how the NAND gate 1609 receiving the output of the respective input buffers to be tested is connected in relation to the respective input terminals. In other words, a test pattern used for the input threshold voltage testing by use of an LSI tester, must be individually prepared for each of products, on the basis of the circuit connection information of each product. As a result, the number of steps for preparing the test pattern will increase the manufacturing cost of the LSI.